Basic knowledge of pattern design
(1) Basic electrical knowledge and design guidelines
-Noise is also electric, and Ohm's law is applied.
The smaller R (Z) of "V = I × R", the smaller V (noise).
-For delicate signals (analog, clock, reset, etc.), wire the pattern width thicker.
Lowers impedance and makes it more resistant to noise.
・ Provide as large a clearance as possible between patterns. At least twice the pattern width is desirable.
It reduces capacitive binding and inducible binding with adjacent patterns and suppresses crosstalk.
・ No antenna wiring is provided.
Designed so that there are no signals, power supplies, sharp angles of GND, and copper foil that stretches like a beard.
The part where the pattern is thin has high impedance, and the noise is picked up and propagated in the board by the behavior like an antenna. Also, be careful as it may pick up noise in an unintended frequency band and oscillate.
-Use the thickest possible wiring for the GND guard, and connect it to the GND solid layer via VIA as much as possible in the middle of the guard.
Since the impedance of the thin GND guard is high, noise is easy to get on, and noise is induced from the GND guard to the signal line to be guarded. The same applies to the GND guard that is not connected to the GND solid layer.
・ Widen the VIA interval and secure the signal / power return path.
Since the circuit of signals and power supplies is up to the point where GND returns and returns to the source, the longer the return, the longer the loop, which causes noise. When the inner layer GND between VIAs is cut off, the return path becomes longer as it wraps around.
-If the number of board layers is small and signal wiring must be wired in adjacent layers, be sure to make the patterns orthogonal.
By making the directions of the magnetic fields in which the pattern is generated orthogonal to each other, the coupling between the magnetic fields is minimized.
(2) Design guidelines for various types of parts and signals
① Decoupling capacitor (decoupling capacitor)
・ Place it in the immediate vicinity of the terminal to be used, and connect it to the supply terminal in the shortest possible pattern.
Connect the GND terminal of the decap and the GND terminal of the semiconductor as short as possible to reduce the inductance loop.
Inductance loop (decap and semiconductor current loop) is small → generated magnetic field is small → noise is small ・ For QFP and BGA type semiconductors, the power supply terminal and the corresponding GND terminal may be set exclusively. , Check the data sheet and circuit diagram of each part, and be careful not to make any mistakes in placement and wiring.
-If multiple capacitors are connected in parallel to one terminal, place the one with the smaller capacity on the terminal side.
The smaller capacity has a faster response speed and is more effective against noise in the high frequency band.
② Oscillator
-The pattern connected to the oscillator, its peripheral circuit components, and the IC should be thick and shortest, and the circumference should be surrounded by GND. The GND is separated from the peripheral GND and one point is connected in the immediate vicinity of the IC.
・ All layers of the inner layer are removed from the pattern directly under the pattern connected to the oscillator and its peripheral circuit components and the IC, and the GND plane for the oscillator is provided only on the opposite side of the oscillator mounting surface.
By reducing the parasitic capacitance, unintentional oscillation, ringing, and waveform blunting are suppressed.
* If the wiring area is small and the above is difficult, we will apply what is possible after consultation within the company.
If there is a request or question from the user, explain the guideline and decide to respond after consultation.
③ SW power supply
・ Connect the SW terminal to the smoothing coil in the shortest time, and make it the minimum thickness.
Since a high-energy (large current) high-frequency voltage is oscillating, a very strong magnetic field is generated, which causes a large amount of noise.
・ Place and wire the GND so that the input side and output side decaps and the GND of the SW power supply IC are the shortest (the loop is small), and connect at one point if possible.
The one-point connection position is preferably the GND terminal position of the output side decap.
④ Signals to watch out for
-Wire delicate signals such as CLK (including SCL), RESET, I2C, and analog signals as thick as possible, and provide a GND guard line that is as thick as possible. Provide GND vias on the guard line as appropriate (every 10 mm).
Even for signals that require control of characteristic impedance, the wider the pattern width, the more resistant to noise and less loss, so consider the layer configuration with the board manufacturer and take appropriate measures.
(3) Precautions for wiring the power supply and GND pattern
Since there are conflicting conditions for the wiring of the power supply pattern, determine the appropriate power supply wiring method (wire or solid power supply, solid power supply size) with reference to the following conditions.
-Current capacity: As a general rule, when using 35 μm copper foil (without plating), design at 1 A / mm (copper foil temperature rise within 20 ° C).
If the above cannot be observed on a high-current board or the like, the rising temperature of the copper foil is calculated and the pass / fail judgment of the pattern width is performed.
It goes without saying that the VIA and pattern width that match the current capacity should be provided, and that the return GND should also have a VIA and pattern width that is equal to or greater than the current capacity.
-Power supply resonance: Since the solid power supply to the unused area oscillates in the frequency band such as the bus clock and oscillator and becomes noise, unnecessary power supply solid is not provided.
-Voltage drop: In the power supply, voltage drop of V = I × R occurs due to the DC resistance of ferrite beads, the resistance of copper foil and VIA, etc.
For power supplies that use low voltage and large current (approximately 1.5V or less and 1A or more), calculate the drop amount and aim for within -1% of the Ref voltage value, and at worst, calculate and design so that it is within -3%. (From the Xilinx FPGA data sheet)
-Pattern heat dissipation: Heat-generating parts such as regulators and DC / DC should be connected to the solid power supply and GND of the inner and outer layers with many VIAs to dissipate heat.
(4) Pattern width commensurate with current capacity, VIA design and wiring resistance value
Required pattern width for each 1 A current at each copper foil thickness. Condition: Copper foil temperature rise 20 ℃ or less
Current capacity and resistance value that can be passed for each through-hole diameter including VIA. Condition: Copper foil temperature rise 20 ℃ or less
* Since the plating thickness in the through hole is more difficult to manage and varies compared to plating on horizontal copper foil, it is recommended to calculate the plating thickness by 70%.
