Lagless power circuit board design
1. Parts placement and pattern design that match the power supply voltage value
Ensuring creepage distance and clearance distance in compliance with safety standards such as JIS, PSE, UL, MIL, IEC, and EN that match the destination.
Design example)
Input DC400V 10A Minimum creepage distance 5.0mm secured Minimum space distance 5.0mm secured Inner and outer layer copper foil 70μm
Secure pattern width of 10 mm
2. Pattern design that matches the current capacity
Select and design the board copper foil thickness, pattern width, and through-hole diameter in consideration of the current value used.
As a general rule, the design rules for each copper foil thickness shown in Table 2.1 apply. (Copper foil temperature rise 20 ℃ or less)
Copper foil thickness can be up to 200 μm
As a general rule, the design rules for each through-hole (hereinafter referred to as TH) diameter shown in Table 2.2 shall be applied.
(Copper foil temperature rise 20 ℃ or less)
3. Pattern design considering power supply and GND quality
(1) Separation of GND Separate the GND of the power supply circuit from the GND of other digital and analog systems.
Connect one point near the output power supply decoupling capacitor that minimizes high-frequency switching noise.
(2) DC power integrity A power supply with a low voltage level will exceed the permissible value even with a voltage drop (IR drop) of several hundred mV, causing malfunctions. Therefore, widen the copper foil area and lower the resistance value. * 1
(3) AC power integrity In order to keep the PDN impedance within the target impedance, place the corresponding decoupling capacitor appropriately. * 1
(4) Suppression of voltage fluctuation (ground bounce) of GND Secures the path and width of the return current.
* 1: PI (Power Integrity) analysis is also available.
4. Pattern design considering parasitic inductance
The inductance of the loop pattern is minimized and switching noise is reduced.
Example) DC / DC using Linear Technology LTC3775
Circuit simulation considering the parasitic component of the board pattern
Input section, SW output pattern is thin and long,
When the parasitic inductance is large → Overshoot, undershoot, and ringing occur in the switching output.
Noise radiation and efficiency degradation occur.
Input section, SW output pattern is thick and short,
When the parasitic inductance is small.
→ No major abnormality is seen in the switching output, and noise radiation and efficiency deterioration are suppressed.
Green waveform: sense
Blue waveform: 1.2V output
Red waveform: switching output
Ideal circuit simulation ignoring the parasitic components of the board pattern